1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, to an internal voltage generation circuit of a semiconductor device, and an operating method thereof, and more particularly, to an internal voltage generation circuit of a semiconductor device that does not include a dead zone operating region and an operating method thereof.
2. Description of the Related Art
As a critical dimension and a cell size of a semiconductor device are reduced, a power supply voltage is also reduced, and accordingly, a design technology for low voltage circumstances is useful.
For example, a semiconductor device includes an internal voltage generation circuit that receives a power supply voltage (VDD) and generates internal voltages to provide to internal circuits of a semiconductor device.
FIG. 1 is a circuit diagram illustrating a conventional internal voltage generation circuit of a semiconductor device.
Referring to FIG. 1, a conventional internal voltage generation circuit of a semiconductor device includes a first internal voltage input buffer 100, a second internal voltage input buffer 120, and an internal voltage driving block 140.
The first internal voltage input buffer 100 is configured to determine a voltage level of a pull-up driving node PU_DRVND as a result of a comparison between a voltage level of an internal voltage (VINT) node and a voltage level of a first reference voltage (VREF1) node.
The second internal voltage input buffer 200 is configured to determine a voltage level of a pull-down driving node PD_DRVND as a result of a comparison between a voltage level of the internal voltage (VINT) node and a voltage level of a second reference voltage (VREF2) node.
The internal voltage driving block 140 is configured to pull-up drive the internal voltage (VINT) node in response to the voltage level of the pull-up driving node PU_DRVND and pull-down drive the internal voltage (VINT) node in response to the voltage level of the pull-down driving node PD_DRVND.
In the conventional internal voltage generation circuit of a semiconductor device, the voltage level of the internal voltage (VINT) node is determined in response to a PMOS transistor DP1 for pull-up driving the internal voltage (VINT) node and an NMOS transistor DN1 for pull-down driving the internal voltage (VINT) node. In many cases, the voltage level of the internal voltage (VINT) node is determined to a voltage level corresponding to an intermediate value between the voltage level of the first reference voltage (VREF1) node and the voltage level of the second reference voltage (VREF2) node.
FIGS. 2A and 2B are graphs illustrating operations of the conventional internal voltage generation circuit of a semiconductor device shown in FIG. 1.
Referring to FIG. 2A, operations of the conventional internal voltage generation circuit of a semiconductor device are divided into three regions depending upon the voltage level of the internal voltage (VINT) node.
In detail, in a pull-up region where the voltage level of the internal voltage (VINT) node is lower than the voltage level of the first reference voltage (VREF1) node, the PMOS transistor DP1 for pull-up driving the internal voltage (VINT) node is turned on such that current from a power supply voltage (VDD) terminal is provided to the internal voltage (VINT) node. Accordingly, the voltage level of the internal voltage (VINT) node rises. In the pull-up region, the NMOS transistor DN1 for pull-down driving the internal voltage (VINT) node is turned off such that current does not flow from the internal voltage (VINT) node to a ground voltage (VSS) terminal.
In a pull-down region where the voltage level of the internal voltage (VINT) node is higher than the voltage level of the second reference voltage (VREF2) node, the NMOS transistor DN1 for pull-down driving the internal voltage (VINT) node is turned on such that current flows from the internal voltage (VINT) node to the ground voltage (VSS) terminal. Accordingly, the voltage level of the internal voltage (VINT) node falls. In the pull-down region, the PMOS transistor DP1 for pull-up driving the internal voltage (VINT) node is turned off such that current is not provided from the power supply voltage (VDD) terminal to the internal voltage (VINT) node.
In a dead zone region where the voltage level of the internal voltage (VINT) node is higher than the voltage level of the first reference voltage (VREF1) node and lower than the voltage level of the second reference voltage (VREF2) node, the NMOS transistor DN1 for pull-down driving the internal voltage (VINT) node is turned off such that current does not flow from the internal voltage (VINT) node to the ground voltage (VSS) terminal, and simultaneously, the PMOS transistor DP1 for pull-up driving the internal voltage (VINT) node is turned off such that current does not flow from the power supply voltage (VDD) terminal to the internal voltage (VINT) node. More specifically, the internal voltage driving block 140 does not perform any operation in the dead zone region, and no current flows from the power supply voltage (VDD) to the internal voltage (VINT) node, and no current flows from the internal voltage (VINT) node to the ground voltage (VSS).
Referring to FIG. 2B, some of the exemplary issues of the conventional internal voltage generation circuit are illustrated.
In detail, as described above with reference to FIG. 2A, in the conventional internal voltage generation circuit, the internal voltage driving block 140 does not perform any operation in the dead zone region. The substantial size of the dead zone region means that the internal voltage driving block 140 does not perform any operation for an increased amount of time. Thus, in order to improve the operation reaction speed of the first and second internal voltage input buffers 100 and 120, the size of the dead zone region is to be reduced.
However, referring to FIG. 2B, due to offset operations of the first and second internal voltage input buffers 100 and 120, both the NMOS transistor DN1 for pull-down driving the internal voltage (VINT) node and the PMOS transistor DP1 for pull-up driving the internal voltage (VINT) node may be turned on such that through current is produced.
Summarizing this, where the offset operations are not caused in the first and second internal voltage input buffers 100 and 120 as shown in FIG. 2A, since both the NMOS transistor DN1 for pull-down driving the internal voltage (VINT) node and the PMOS transistor DP1 for pull-up driving the internal voltage (VINT) node are turned off in the dead zone region, the through current is not produced.
However, as shown in FIG. 2B, if the first and second internal voltage input buffers 100 and 120 perform the offset operations, a phenomenon may occur where there are periods in which the voltage levels of the pull-up driving node PU_DRVND and the pull-down driving node PD_DRVND overlap with each other as the voltage levels of the pull-up driving node PU_DRVND and the pull-down driving node PD_DRVND shift toward each other. In this regard, in the event that the voltage level of the internal voltage (VINT) node corresponds to one half of the voltage level of a power supply voltage VDD, both the NMOS transistor DN1 for pull-down driving the internal voltage (VINT) node and the PMOS transistor DP1 for pull-up driving the internal voltage (VINT) node are turned on, and a through current phenomenon occurs in which a large amount of current flows from the power supply voltage (VDD) terminal through the PMOS transistor DP1 and the NMOS transistor DN1 to the ground voltage (VSS) terminal.
If the through current phenomenon occurs in this way, current use of a semiconductor device abruptly increases, and as a result, the power consumption of the semiconductor device increases. Therefore, in the conventional art, the dead zone region equal to or greater than several tens of mV is maintained.
As a consequence, due to the presence of the dead zone region, the reaction speed of the internal voltage generation circuit is substantially slowed down, and the performance of the semiconductor device may deteriorate.